VLSI chip hot-spot minimization using nanotubes

ABSTRACT

The invention relates to a semiconductive device comprising a die with at least one defined hot-spot area lying in a plane on the die and a cooling structure comprising nanotubes such as carbon nanotubes extending in a plane different than the plane of the hot-spot area and outwardly from the plane of the hot-spot area. The nanotubes are operatively associated with the hot-spot area to decrease any temperature gradient between the hot-spot area and at least one other area on the die defined by a temperature lower than the hot-spot area. A matrix material comprising a second heat conducting material substantially surrounds the nanotubes and is operatively associated with and in heat conducting relation with the other area on the die defined by a temperature lower than the hot-spot area. The heat conductivity of the nanotubes is greater than the heat conductivity of the matrix material, with the distal ends of the nanotubes exposed to present a distal surface comprising the first heat conducting means for direct contact with a medium comprising a cooling fluid. The inventors also disclose processes for manufacturing and using the device and products produced by the processes.

FIELD OF THE INVENTION

The field of the invention comprises nanotube cooling membersincorporated into semiconductor devices, and very large scale integrated(“VLSI”) semiconductor devices having high temperature areas or“hot-spots.” The arrangement of the cooling members with other heatconductive materials minimizes or substantially eliminates thermal ortemperature gradients between hot-spots and cooler areas on the device.

RELATED ART

The so-called “silicon revolution” spurred the development of faster andlarger computers beginning in the early 1960's, with the industrypredicting rapid growth because of the increasing numbers of transistorspacked into integrated circuits, estimating transistors on integratedcircuits would double every 2 years. Experience has shown that since1975 the number of transistors on a semiconductor chip doubled aboutevery 18 months.

The semiconductor industry experienced an extremely active period ofinnovation in the 1970's in the areas of circuit design, chiparchitecture, design aids, processes, tools, testing, manufacturingarchitecture and manufacturing discipline. The combination of thesedisciplines enabled the industry to enter into the VLSI era with theability to mass-produce chips with 100,000 transistors per chip at theend of the 1980's after beginning the large scale Integration (“LSI”)era in 1970 with only 1,000 transistors per chip. (Carre, H. et al.“Semiconductor Manufacturing Technology at IBM”, IBM J. RES. DEVELOP.,VOL. 26, no. 5, September 1982). Mescia et al. also describe theindustrial scale manufacture of these VLSI devices. (Mescia, N.C. et al.“Plant Automation in a Structured Distributed System Environment”, IBMJ. RES. DEVELOP., VOL. 26, no. 4, July 1982).

Chen, U.S. Pat. No. 6,951,001, notes that continued scaling of thecomplementary metal oxide semiconductor (“CMOS”) fabrication processincreases the number of devices on a VLSI chip but causes “within-die”variations that can become significant problems such as L_(e) (theeffective channel Length) and V_(t) (threshold voltage) as well assupply voltage and temperature variations. Within-die variations canalso cause on-chip signal timing uncertainties. Conventional timinganalysis for VLSI chips uses different values for process, voltage andtemperature corners (maximum allowable combinations for these values)for maximum and minimum signal delay analysis. This approach often leadsto “overdesigning,” which may cause increasingly high power requirementsand reliability problems. High power requirements can lead tooverheating.

The introduction of IBM's Power6™ chip due in the middle of 2007, notedthat “miniaturization has allowed chipmakers to make chips faster bycramming more transistors on a single slice of silicon, to the pointwhere high-end processors have hundreds of millions of transistors. Butthe process also tends to make chips run hotter, and engineers have beentrying to figure out how to keep shrinking chips down while avoidingthem frying their own circuitry.”(http://www.nytimes.com/reuters/technology/tech-ibm-power.html?pagewanted=print(Feb. 7, 2006))

Technology scaling of semiconductor devices to 90 nm and below hasprovided many benefits in the field of microelectronics, but hasintroduced new considerations as well. While smaller chip geometriesresult in higher levels of on-chip integration and performance, highercurrent and power densities, increased leakage currents, and low-kdielectrics with poorer heat conductivity occur that present newchallenges to package and heat dissipation designs.

Sub-90 nm technologies also have to address on-die temperaturevariations as much as 50° C., or even higher in metal layers on thesemiconductor chip since such severe temperature gradients can impactboth performance and the reliability of the device, such as signaltiming, clock skew, cross-talk noise, voltage drop, andmedian-time-to-failure of the device. (Chandra, Rajit, “Automotiveelectronics need thermal-aware IC design” Automotive Design Line, (Jun.13, 2005);http://www.automotivedesignline.com/GLOBAUelectronics/designline/shared/article/showArticle.jhtml?articled=164302553&pgno=1).

One approach that addresses on-chip hot-spots involves a temperatureaware design methodology for identifying potential problem areas, andusing this input during the physical design phase in the placement ofthe cells on the die. Chandra, supra. While this approach may reducesome hot-spots and temperature gradients, it does not seem likely thatit will eliminate the problem, as for example, a central processing unit(“CPU”) core will draw more current than a dynamic random access memory(“DRAM”) memory bank.

SUMMARY OF THE INVENTION

The foregoing indicates a need for a semiconductor device, such as aVLSI device, that minimizes or substantially eliminates thermalgradients in the device in order to avoid the various problemsassociated with these gradients, and a need for a process to make such adevice.

Accordingly the present invention provides such a device or devices andprocesses for manufacturing them that addresses these needs to not onlyprovide advantages over the related art, but also substantially obviateone or more of these and other limitations and disadvantages ofsemiconductor devices, particularly VLSI devices. The invention alsocomprises products produced by such processes and processes forminimizing temperature gradients on such devices.

The description that follows sets forth features and advantages of theinvention, apparent not only from the description, but also bypracticing the invention. The written description, including theabstract of the disclosure and the claims and drawing as filed or as anyof the foregoing may be subsequently amended will set forth additionalfeatures and advantages of the invention, and particularly point out theobjectives and other advantages of the invention, showing how they maybe realized and obtained.

To achieve these and other advantages, and in accordance with thepurpose of the invention, as embodied and broadly described herein, theinvention comprises a semiconductor device such as a VLSI device thatminimizes or eliminates hot-spots and/or temperature gradients in thedevice, such as the die surface by using heat conductor means comprisinga plurality of nanotube means positioned on the device to conduct heataway from such hot-spots. The terms “temperature gradient” and “thermalgradient” mean the difference in temperature between the hot-spot andanother area or areas on the semiconductor device. The use of suchnanotubes takes advantage of their extremely high heat conductioncapability along their long axis compared to the metals currently usedto remove heat from these devices, thus minimizing or eliminatingon-chip temperature gradients. The inventors achieve these advantages bygrowing nanotubes selectively on the hot-spot areas while usingconventional heat conductors for the relatively cooler areas of thechip.

Non-selective growth on the device, i.e., covering the entire surface ofthe device with nanotubes would have little or no effect in eliminatingor minimizing hot-spots or thermal gradients on the device since therate and degree of cooling the entire surface would be substantially thesame, so that the hotter areas would still remain relatively hotter andthe other areas relatively cooler even though the temperatures of bothwould be reduced. Thus selective placement of the nanotubes on thedevice in combination with placement of conventional heat conductors incomplementary areas of the device amounts to a key element in obtainingthe advantages of the invention.

Carbon nanotubes comprise strips of graphite sheet rolled into tubes afew nanometers in diameter and up to hundreds of micrometers (microns or“μm”) in length. Den et al. U.S. Pat. No. 6,979,244 describes these assheets of carbon hexagonal meshes parallel to and extending 3600 arounda vertical axis producing a graphite network of hexagonal rings havingthe highest heat conductivity of any material (6000 W/mK compared to 400W/mK for copper).

Bethume et al., U.S. Pat. No. 5,424,054, describes hollow carbon fibersor nanotubes having a cylindrical wall comprising a single layer ofcarbon atoms and a process for producing such fibers. Other referencesdisclose the production of nanotubes, including Geohegan et al. U.S.Pat. No. 6,923,946; Ma et al. U.S. Pat. No. 6,936,565; Arik et al. U.S.Pat. No. 6,864,571; Dai et al., U.S. Pat. No. 6,346,189; Keesman et al.,U.S. Pat. No. RE38,223; Brorson, et al., U.S. Pat. No. 6,887,453; Mo, J.et al. “Integrated Nanotube Cooler for Microelectronic Applications,”Proceedings of the IEEE CPMT Conference on Electronics ComponentsTechnology (ECTC55), May 30-Jun. 3, 2005, Orlando, USA, pp. 51-54;Berber, S. et al. “Unusually High Thermal Conductivity of CarbonNanotubes,” Physical Review Letter, vol. 84, No. 20, pp. 4613-16, 2000;Fan, S. S. et al., “Self Oriented Regular Arrays of Carbon Nanotubes andTheir Field Emission Properties,” Science, Vol. 283, pp. 512-14, (1999);Ma et al., U.S. Pat. No. 6,936,565; Den et al. U.S. Pat. No. 6,979,244;Brave New Nanoworld, p. 3,http://www.ornl.gov/info/ornlreview/rev32_(—)3/brave.htm (Oak RidgeNational Laboratory); whereas Den et al.; and Brave New Nanoworld(supra) describe methods for making multiwall nanotubes of carbon.lijima, S., Nature 1991, 354, 56; Ajayan, P. M., et al. Nature 1992,358, 23; Ebbesen, T. W., Nature 1992, 358, 20; Gao, et al., J. Phys.Chem. B 2000, 104, 1227-1234; also describe methods for making nanotubesand Margulis, L. et al., Journal of Microscopy 1996, 181, 68-71identifies helical nanotubes. All of the foregoing references teachnanotubes falling within the scope of the invention.

BRIEF DESCRIPTION OF THE DRAWING

The accompanying drawing, incorporated in and which constitutes a partof this specification, illustrates single and multiple embodiments ofthe invention, and together with the other parts of the specification,serves to explain the objects, advantages and principles of theinvention.

In the drawing the Figure comprises a side elevation in cross section ofa semiconductor device employing nanotubes for the elimination orminimization of hot-spots on the device.

DETAILED DESCRIPTION OF THE INVENTION

The present invention comprises a semiconductive device having asemiconductor die structure known in the art. The device, and the die inparticular, has at least one defined hot-spot area lying in a plane withcooling means comprising a plurality of nanotube means extending in aplane different than the plane of the hot-spot area and outwardly fromthe plane of the hot-spot area. The term “plane” as used herein includesflat as well as curvilinear planes. In addition to the foregoing, theterm “plane” applies to nanotube means lying in a single plane ormultiple planes extending substantially from the hot-spot or at a pointalong the length of the nanotube means. The defined hot-spot areacomprises an area identified by thermal analysis that shows atemperature higher than the area or areas surrounding the hot-spot.

The nanotubes can be substantially perpendicular to the plane of thehot-spot, i.e., at substantially a 90° angle, to the plane of thehot-spot, or anywhere from about 70° to about 90°, or about 80° to about90° to the plane of the hot-spot. The related art shows in this respectthat the principle orientation of the nanotubes may not only be straightwalled but also include configurations where the wall bends at its upperreaches or may branch, or may take on other configurations. Thenanotubes also comprise self oriented (straight up and down) structureswith the individual nanotubes being substantially parallel to oneanother. Fan, S. S. et al., “Self Oriented Regular Arrays of CarbonNanotubes and Their Field Emission Properties,” Science, Vol. 283, pp.512-14, (1999) illustrates nanotube configurations of this type whichfall within the scope of the invention. They may also compriseoff-vertical arrays or dendritic or forest arrays (Fan et al. FIG. 6),as well as fin projections, or porous two-dimensional arrays, or porousstructures as disclosed in FIGS. 2, 4, and 6 of Mo, J. et al.“Integrated Nanotube Cooler for Microelectronic Applications,”Proceedings of the IEEE CPMT Conference on Electronics ComponentsTechnology (ECTC55), May 30-Jun. 3, 2005, Orlando, USA, pp. 51-54, andmay include bending, and/or intertwining deviations from generallyaligned and straight nanotube as described by Arik et al. U.S. Pat. No.6,864,57. The nanotubes may also comprise fin projections, or poroustwo-dimensional arrays, or porous structures as disclosed in FIGS. 2, 4,and 6 of Mo, J. et al. (supra) and may include bending, and/orintertwining deviations from generally aligned and straight nanotubeorientations as described by Arik et al. U.S. Pat. No. 6,864,571. Thepresent invention includes all of the foregoing configurations.

The invention comprises a plurality of these nanotubes, i.e., clusterssomewhere from substantially tens, to hundreds, to thousands, to tens ofthousands, or hundreds of thousands or more as distinguished fromstructures having only 1, or 2 or 3 extending from the surface asdisclosed by Dai et al., U.S. Pat. No. 6,346,189 or Den et al. U.S. Pat.No. 6,979,244.

The nanotubes may also comprise helical structures, sometimes referredto as nanosprings or zig-zag structures and are of special interestsince they have greater surface area per unit length, whether extendedor unextended, as compared to nanotubes that extend substantially in anon-helical or non zig-zag manner. The extra surface area per unitlength not only of nanosprings, but also dendritic or forest arrays, finprojections, and porous two-dimensional arrays, or porous structures,all of which fall within the scope of the invention, presentconfigurations that will impact on the convective or conductive coolingproperties of the nanotubes.

Den et al. U.S. Pat. No. 6,979,244 describes an arc discharge processfor manufacturing these helical carbon nanotubes having an innerdiameter of about 4 to about 34 nm and about 1 μm in length as well as amultilayer helix having an inner diameter of about 0.34 nm produced byan arc discharge process. Laser evaporation produces a “rope” shapedcarbon nanotube. Gao, et al., J. Phys. Chem. B 2000,104, 1227-1234 alsodescribes these so-called nanotube zig-zag and helical structures andgives methods for manufacturing them. Arik et al. U.S. Pat. No.6,864,571 discloses these helical structures, referring to them as“nanosprings.” Ma et al. U.S. Pat. No. 6,936,565 describes a process formanufacturing these nanosprings, as well as nanotubes comprisingphysical vapor deposition such as glancing angle deposition or “GLAD.”

These nanotubes comprise single wall or multiwall structures up toseveral centimeters in length as described by Brorson, et al., U.S. Pat.No. 6,887,453 and can have up to about 8 to about 10 or more carbonlayers. Den et al. U.S. Pat. No. 6,979,244 also describes thesemultiwall carbon nanotube structures up to about 1 μm in length, eithersingle wall or multiwall, and in some instances surrounded by amorphouscarbon, as well as methods for their manufacture, e.g., by arcdischarge, laser evaporation, pyrolysis and plasmas.

Keesman et al., U.S. Pat. No. RE38,223; Ajayan and lijima, Nature, 361,p. 333; Geohegan, U.S. Pat. No. 6,923,946; Arik et al. U.S. Pat. No.6,864,571; Lieber et al. U.S. Pat. No. 5,897,945; Ma et al. U.S. Pat.No. 6,936,565; and Margulis, L. et al., Journal of Microscopy 1996, 181,68-71 describe variations of these nanotube structures all of which fallwithin the scope of the invention.

Production of these nanotube means employs processes known in the art,such as the processes described in the foregoing and followingreferences and come within the scope of this invention. The manufactureof carbon nanotube means employs catalysts for the pyrolysis of a carboncontaining material, such as for example ethylene or other organiccompounds in the presence of a catalyst such as Ni or Co. Den et al.U.S. Pat. No. 6,979,244, citing WO 89/07163 mentions Fe optionally withMo, Cr, Ce or Mn as suitable catalysts, whereas Dai et al., U.S. Pat.No. 6,346,189 discloses the use of Fe, Mo, Ru Mo, Co, Ni, Zn, or Ru andpreferably the oxides of Fe, Mo, Ru, and Zn, e.g., Fe₂O₃ having aparticle size of from about 1 μm to about 5 μm as catalysts. Geohegan etal. U.S. Pat. No. 6,923,946 describe Fe, Ni, Co, Rh, Pd or alloysthereof as catalysts, and Mo, J. et al. “Integrated Nanotube Cooler forMicroelectronic Applications,” Proceedings of the IEEE CPMT Conferenceon Electronics Components Technology (ECTC55), May 30-Jun. 3, 2005,Orlando, USA, pp. 51-54 employ Fe, Ni, and Co for the catalyticconversion of carbon materials into these nanotubes.

The cooling means comprising the nanotube means is operativelyassociated with the hot-spot area to decrease any temperature gradientbetween the hot-spot area and at least one other area on the die definedby a temperature lower than the hot-spot area, which is an area set outby thermal analysis that has a temperature lower than the hot-spot areaor areas. These gradients may comprise temperature differences anywherefrom about 19° C. to about 45° C., or about 50° C. to about 80° C., orabout 25° C. to about 100° C.

“Operatively associated with” also includes those instances where thehot-spot is beneath another layer or layers on the die or enveloped by apackaging material so that heat from the hot-spot is presented to theexterior surface of the other layer or layers or packaging material. Thecooling means in that case will be placed on this heated exterior insubstantially the same way as they are placed on the hot-spot on the diearea.

In one embodiment an adhesion layer secures the catalyst for forming thenanotubes, and as a result the nanotubes as well to the surface of thedie. This adhesion layer also helps to join the matrix material to thedie. The adhesion layer comprises a boron material or silicon materialor metal material, the boron material and the silicon materialcomprising elemental boron and silicon or compounds of boron and siliconrespectively, whereas the metal material comprises both elemental metalsas well as metal compounds and alloys and combinations of a boronmaterial or silicon material or metal material.

Examples of adhesion layers comprise Cr or Ta layers. Fan, S. S. et al.,“Self Oriented Regular Arrays of Carbon Nanotubes and Their FieldEmission Properties,” Science, Vol. 283, pp. 512-14, (1999), however,describe growing these nanotubes directly on a silicon surface withoutemploying an adhesion layer, this process also falling within the scopeof one aspect of the invention.

These cooling means are substantially surrounded by, and in oneembodiment, are substantially contiguous with a matrix material on thesurface of the device, such as the surface of the die. “Substantiallycontiguous” in this context means touching the matrix at any point ortouching the matrix at a plurality of points, or along the full lengthof the nanotube means. The matrix comprises a second heat conductingmaterial and is operatively associated with and in a heat conductingrelation with the other area on the die defined by a temperature lowerthan the hot-spot area.

“Operatively associated with” in this context means the matrix materialis contiguous at several points or through the whole area of the matrixon the other area of the device such as the die defined by a temperaturelower than the hot-spot area, device layers above this area, orpackaging material enveloping the device, directly or through anadhesion layer or such layers on such other area on the device, wherethe adhesion layer comprises a metal material, or boron material, orsilicon material, or device components or packaging material thatenvelops the die. “Metal material” in this context includes elementalmetal or metals, metal alloys or metal compounds such as oxides,nitrides, carbides and the like, and “silicon material,” and “boronmaterial” have the same meaning as previously given.

The matrix material comprises a layer of the second heat conductingmaterial which in some instances comprises a material that is relativelythick, e.g., anywhere from about 1 μm to about 20 μm, or about 20 μm toabout 200 μm, or about 100 μm to about 10000 μm thick, and comprises notonly Cu, but also Zr, Nb, Ta, Mo, Zn or Al, and alloys thereof with oneanother or other elements. Den et al. U.S. Pat. No. 6,979,244 alsodescribes these elements as conductive layers in semiconductor devices.Other materials with lower heat conductivity than copper can also beused in cases where the temperature gradients are too large for thematrix/carbon nanotube combinations to eliminate or minimize temperaturegradients as described above. Such materials may comprise, but are notlimited to, metal oxides or nitrides, silicon or boron nitrides, andorganosilicate glasses.

The heat conductivity of the first heat conducting material (i.e., thematerial from which the nanotube means is formed) is greater than theheat conductivity of the second heat conducting material (i.e., thematerial from which the matrix is made). In another aspect of theinvention, the distal ends of the nanotubes are substantially free ofthe matrix material or other material, i.e., the distal ends of thenanotube means are provided with a surface comprising said first heatconducting material to make said distal ends available for directcontact with a medium comprising a cooling medium such as a coolingfluid, i.e., a gas or a liquid, or other cooling medium such as a pastecontaining aluminum powder and/or flake.

In some instance matrix material might project over the distal ends andrequires employing a process to substantially remove the matrix, e.g.,chemical-mechanical polishing. In other instances providing a mask overthe distal ends during manufacture of the device to substantiallyprevent other materials from attaching to the surface of the distal endscan have the same effect. Removal of this mask upon the completion ofthe manufacturing process will make the surface of the distal endsavailable for direct contact with a medium comprising a heat exchangemedium such as a heat exchange fluid. This makes the distal ends of thenanotube means available for direct contact with a medium comprising aheat exchange medium.

The nanotube means in some embodiments are substantially parallel to oneanother; linear or helical; lie in a plane perpendicular to the plane ofthe hot spot; comprise carbon; or the nanotubes may comprise single wallor multi-wall nanotubes; or the first heat conducting material comprisescarbon and the second heat conducting material comprises a metal; or thedevice comprises a VLSI device. In another embodiment, the device may becharacterized not only by any one of the foregoing features, but alsoany combination of these features.

The Figure illustrates one aspect of the invention, and shows a sideelevation in section of a semiconducting device 10 comprising part of aVLSI device that comprises silicon die 12 coated with an adhesion layer14 comprising either Cr or Ta, and a catalyst 16 comprising Ni or Co forproducing carbon nanotubes applied selectively to high temperatureregions or hot-spots 26 extending to and forming hot-spot areas on thesurface of die 12. Carbon nanotube clusters 20 grown on the catalystextend substantially perpendicular from the die 12 with distal ends inan open region above the device 10. The distal ends of carbon nanotubes20 are substantially free of extraneous materials and comprise carbon. Amatrix material comprising copper layer 18 substantially surrounds andis substantially contiguous with the outer regions of the sidewalls ofnanotube clusters 20. Interconnect layer 22 comprises a conventionalinterconnect material known in the art and connects silicon die 12 to aball grid array socketing system 24 known in the art.

The high temperature regions 26 that form the hot-spot areas aresurrounded by regions at a lower temperature when the device is in use.This initially produces a temperature gradient between the hot-spotareas and the other areas. The carbon nanotubes 20 cool the hot-spotareas at a faster rate than copper matrix 18 cools the other areasbecause of the higher heat conductivity of the nanotube clusters 20compared to the copper matrix 18, thereby substantially minimizing oreliminating any temperature gradient that develops on the surface ofdevice 10.

When in use, the device 10 has a region above it comprising a heatexchange medium such as a heat exchange fluid in heat exchange relationwith the distal ends of the carbon nanotube clusters 20. The heatexchange fluid can comprise air, nitrogen, a rare gas, a refrigerantgas, e.g., a fluorochloro carbon, or fluorocarbon known in the art, orother gas, or a liquid such as water or an organic liquid, e.g., aketone, ether, ester, or alcohol also known in the art. In oneembodiment, the heat exchange fluid is circulated over the distal endsof nanotubes 20, passed to a heat exchanger, and recirculated to thedevice 10. A once through system can be employed comprising passing aheat exchange fluid such as air or nitrogen over the distal ends ofnanotubes 20 and exhausting it away from the device 10.

EXAMPLE

A semiconducting device such as a VLSI device is constructed in a mannerwell known in the art. The hot-spot areas or pattern of the on-diecircuits are identified as well as the other areas on the die having atemperature lower than the hot spot areas, using the method andapparatus described by Hamann, H. F. et al. “Power DistributionMeasurements of the Dual Core PowerPC™970 MP Microprocessor,” ISSCC Dig.Tech Papers, p. 534, February 2006.

A lithographic mask corresponding to the hot-spot regions is fabricatedfollowed by deposition of a Cr or Ta adhesion layer for the subsequentcatalyst layer. Using the lithographic mask and standard lithographictechniques, a Ni, or Co, or Fe catalyst layer for nanotube growth ispatterned over the adhesion layer to correspond to the hot-spot regions.Fan, S. S. et al., “Self Oriented Regular Arrays of Carbon Nanotubes andTheir Field Emission Properties,” Science, Vol. 283, pp. 512-14, (1999)and Mo, J. et al. “Integrated Nanotube Cooler for MicroelectronicApplications,” Proceedings of the IEEE CPMT Conference on ElectronicsComponents Technology (ECTC55), May 30-Jun. 3, 2005, Orlando, USA, pp.51-54 describe processes using masks. The substrate is then insertedinto a carbon nanotube growth chamber to produce carbon nanotubeclusters on the catalyst patterns using growth conditions known in theart that promote growth of vertically aligned, i.e., perpendicular tothe substrate, carbon nanotubes.

A layer of copper slightly greater in thickness than the height of thecarbon nanotube clusters is then deposited over the entire structure bymeans of electro deposition or other methods well known in the art, andthe copper layer subjected to chemical mechanical polishing, also wellknown in the art, to expose the distal ends of the nanotube clusterssufficiently to allow the carbon surfaces of the clusters to besubstantially in direct heat exchange contact with a medium comprising aheat exchange fluid or other heat exchange medium.

Throughout this specification, the inventors have set out equivalents,such as equivalent elements, materials, compounds, compositions,conditions, processes, structures and the like, and even though set outindividually, also include combinations of these equivalents such as thetwo component, three component, or four component combinations.

Additionally, the various numerical ranges describing the invention asset forth throughout the specification also include any combination ofthe lower ends of the ranges with the higher ends of the ranges, and anysingle numerical value within a range, or any single numerical valuewithin a range that will reduce the scope of the lower limits of therange or the scope of the higher limits of the range, and ranges fallingwithin any of these ranges.

The terms “about,” or “substantial,” or “substantially” as applied toany parameters herein, such as a numerical value, including values usedto describe numerical ranges, means slight variations in the parameter,or that which is largely or for the most part entirely specified. Theinventors also employ the terms “about,” “substantial,” and“substantially,” in the same way as a person with ordinary skill in theart would understand them or employ them. In another embodiment, theterms “about,” “substantial,” or “substantially,” when employed todefine numerical parameters include, e.g., a variation up to fiveper-cent, up to ten per-cent, or up to 15 per-cent, or somewhat higheror lower than the upper limit of five per-cent, ten per-cent, or 15per-cent. The term “up to” that defines numerical parameters means zeroor a miniscule number, e.g. 0.001.

All scientific journal articles and other articles as well as patentsthat this written description mentions including the referencesadditionally cited in such scientific journal articles and otherarticles, and such patents, are incorporated herein by reference intheir entirety.

Although the inventors have described their invention by reference tosome embodiments, they do not intend that such embodiments should limittheir invention, but that other embodiments encompassed by the doctrineof equivalents are intended to be included as falling within the broadscope and spirit of the foregoing written description, the Abstract ofthe Invention, the drawing, and the claims.

1. A semiconductive device comprising a die, said device having: (a) atleast one defined hot-spot area lying in a plane on said die; (b)cooling means comprising a plurality of nanotube means composed of afirst heat conducting material and extending in a plane different thanthe plane of said hot-spot area and outwardly from the plane of saidhot-spot area, said nanotube means operatively associated with saidhot-spot area to decrease any temperature gradient between said hot-spotarea and at least one other area on said die defined by a temperaturelower than said hot-spot area; (c) said nanotube means beingsubstantially surrounded by a matrix material comprised of a second heatconducting material operatively associated with and in heat conductingrelation with said other area on said die defined by a temperature lowerthan said hot-spot area; (d) the heat conductivity of said first heatconducting material being greater than the heat conductivity of saidsecond heat conducting material; (e) the distal ends of said nanotubemeans comprising said first heat conducting material, and positioned fordirect contact with a medium comprising a heat exchange medium.
 2. Thedevice of claim 1 wherein said nanotube means substantially: (a) areparallel to one another; (b) are linear or helical; (c) areperpendicular to the plane of said hot spot; and (d) comprise carbon;(e) said heat exchange medium comprises a heat exchange fluid; and (f)said nanotubes comprise single wall or multi-wall nanotubes.
 3. Thedevice of claim 2 wherein said first heat conducting material comprisescarbon and said second heat conducting material comprises a metal. 4.The semiconducting device of claim 2 comprising a VLSI device.
 5. Aprocess for providing cooling means on the surface of a semiconductivedevice having a die comprising: (a) defining at least one hot-spot arealying in a plane on said die; (b) defining another area on said diehaving a temperature lower than said hot-spot area; (c) forming coolingmeans comprising a plurality of nanotube means on said die and composedof a first heat conducting material; said nanotube means extending in aplane different than the plane of said hot-spot area and outwardly fromthe plane of said hot-spot area, said nanotube means formed so as to beoperatively associated with said hot-spot area to decrease anytemperature gradient between said hot-spot area and said area on saiddie having a temperature lower than said hot-spot area; (d)substantially surrounding said nanotube means with a matrix material sothat said matrix material substantially extends over and is operativelyassociated with the surface of said die and in heat conducting relationwith at least one of said areas on said die defined by a temperaturelower than said hot-spot area, said matrix material composed of a secondheat conducting material, said first heat conducting material having aheat conductivity higher than said second heat conducting material; (e)providing the distal ends of said nanotube means with a surfacecomprising said first heat conducting material to make said distal endsavailable for direct contact with a medium comprising a heat exchangemedium.
 6. The process of claim 5 wherein said nanotube meanssubstantially: (a) are parallel to one another; (b) are linear orhelical; (c) are perpendicular to the plane of said hot spot; and (d)comprise carbon; (e) said heat exchange medium comprises a heat exchangefluid; and (f) said nanotubes comprise single wall or multi-wallnanotubes.
 7. The process of claim 6 comprising forming said first heatconducting material from a material comprising carbon and said secondheat conducting material from a material comprising a metal.
 8. Theprocess of claim 6 wherein said semiconducting device comprises a VLSIdevice.
 9. A process for providing cooling means on the surface of asemiconducting device having a die comprising: (a) defining by thermalanalysis, at least one hot-spot area lying in a plane on said die; (b)defining by thermal analysis, at least one other area on said die havinga temperature lower than said hot-spot area; (c) fabricating a maskcorresponding to said hot-spot area; (d) selectively applying to thesurface of said die by means of said mask, a catalyst to define acatalyst area corresponding to said hot-spot area and thereby produce asemiconductive device having a die with a selectively catalyzed surface;said catalyst selected to promote the growth of a plurality of heatconducting nanotube means; (e) growing said nanotube means from a firstheat conducting material and on said selectively catalyzed area toextend in a different plane than the plane of said hot-spot area andoutwardly form the plane of said hot-spot area, said nanotube meansbeing operatively associated with said hot-spot area to decrease anytemperature gradient between said hot-spot area and said area on saiddevice having a temperature lower than said hot-spot area; (f)depositing a second heat conducting material on the surface of said dieto form a matrix to surround said nanotube means, said second heatconducting material extending to and operatively associated with saidother area on said die having a temperature lower than said hot-spotarea to conduct heat away from said other area, said nanotube means madefrom said first heat conducting material having a higher heatconductivity than said matrix made from second heat conducting material;(g) sufficiently removing any of said second heat conducting materialthat extends above the distal ends of said nanotube means to make saiddistal ends available for direct contact with a medium comprising a heatexchange medium.
 10. The process of claim 9 wherein prior to selectivelyapplying said catalyst layer to the surface of said die, the step ofapplying a metal adhesion layer to the surface of said die.
 11. Theprocess of claim 9 wherein said nanotube means substantially: (a) areparallel to one another; (b) are linear or helical; (c) areperpendicular to the plane of said hot spot; and (d) comprise carbon;(e) said heat exchange medium comprises a heat exchange fluid; and (e)said nanotube comprises single wall or multi-wall nanotube.
 12. Theprocess of claim 11 comprising forming said nanotube means from amaterial comprising carbon and said matrix from a material comprising ametal.
 13. The process of claim 11 wherein said semiconducting devicecomprises a VLSI device.
 14. A product produced by the process of claim5.
 15. A product produced by the process of claim
 9. 16. A process forcooling the surface of a semiconductive device having a die comprising:(a) defining at least one hot-spot area lying in a plane on said die;(b) defining another area on said die having a temperature lower thansaid hot-spot area; (c) forming cooling means comprising a plurality ofnanotube means on said die that extend in a plane different than theplane of said hot-spot area and outwardly from the plane of saidhot-spot area, said nanotube means formed so as to be operativelyassociated with said hot-spot area to decrease any temperature gradientbetween said hot-spot area and said area on said die having atemperature lower than said hot-spot area, said nanotube means composedof a first heat conducting material; (d) substantially surrounding saidnanotube means with a matrix material so that said matrix materialsubstantially extends over and is operatively associated with thesurface of said die and in heat conducting relation with at least one ofsaid areas on said die defined by a temperature lower than said hot-spotarea, said matrix material composed of a second heat conductingmaterial, said first heat conducting material having a heat conductivityhigher than said second heat conducting material; (e) providing thedistal ends of said nanotube means with a surface comprising said firstheat conducting material to make said distal ends available for directcontact with a medium comprising a heat exchange medium. (e contactingsaid distal ends with said medium comprising a heat exchange medium,said heat exchange medium being at a temperature lower than thetemperature of said distal ends.
 17. The process of claim 16 whereinsaid nanotube means substantially: (a) are parallel to one another; (b)are linear or helical; (c) are perpendicular to the plane of said hotspot; and (d) comprise carbon; (e) said cooling medium comprises acooling fluid; and (f) said nanotube comprises single wall or multi-wallnanotube.
 18. A process for cooling the surface of a semiconductingdevice having a die comprising: (a) defining by thermal analysis, atleast one hot-spot area lying in a plane on said die; (b) defining bythermal analysis, at least one other area on said die having atemperature lower than said hot-spot area; (c) fabricating a maskcorresponding to said hot-spot area; (d) selectively applying to thesurface of said die by means of said mask, a catalyst to define acatalyst area corresponding to said hot-spot and thereby produce asemiconductive device having a die with a selectively catalyzed surface;said catalyst selected to promote the growth of a plurality of heatconducting nanotube means; (e) growing said nanotube means from a firstheat conducting material and on said selectively catalyzed area toextend in a different plane than the plane of said hot-spot area andoutwardly form the plane of said hot-spot area, said nanotube meansbeing operatively associated with said hot-spot area to decrease anytemperature gradient between said hot-spot area and said area on saiddevice having a temperature lower than said hot-spot area; (f)depositing a second heat conducting material on the surface of said dieto form a matrix to substantially surround said nanotube means, saidsecond heat conducting material extending to and operatively associatedwith said other area on said die having a temperature lower than saidhot-spot area to conduct heat away from said other area, said nanotubemeans made of said first heat conducting material having a higher heatconductivity than said matrix formed from said second heat conductingmaterial; (g) sufficiently removing any of said second heat conductingmaterial that extends above the distal ends of said nanotube means tomake said distal ends available for direct contact with a mediumcomprising a heat exchange medium; (h) contacting said distal ends withsaid medium comprising a heat exchange medium, said heat exchange mediumbeing at a temperature lower than the temperature of said distal ends.19. The process of claim 18 wherein said nanotube means substantially:(a) are parallel to one another; (b) are linear or helical; (c) areperpendicular to the plane of said hot spot; and (d) comprise carbon;(e) said heat exchange medium comprises a heat exchange fluid; and (f)said nanotubes comprise single wall or multi-wall nanotubes.
 20. Theprocess of claim 19 wherein said semiconducting device comprises a VLSIdevice.